Wei-Min Chao

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A 5mW MPEG4 SP encoder is implemented on a 7.7mm<sup>2</sup> die in 0.18mum CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption
To satisfy the high quality image compression requirement, the new JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 times 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed(More)
This paper presents a cost-effective platform architecture design for MPEG-4 video coding. A fast motion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression pcrformance and design cost. An efficient block-level scheduling for texture coding(More)
An MPEG-4 video coding SOC design is presented. We adopt a platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented to provide a compromise between compression performance and design cost. The proposed data reuse scheme reduces the(More)
In this paper, the bitstream parsing analysis and an efficient and flexible hitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing.(More)
A cost-effective hardware architecture of integer, half, and quanerpel motion estimation for MPEG-4 Advanced Simple Profile is proposed in this paper. Three-step hierarchy scheme is employed to cope with different pixel accuracy. For integer-pel estimation, the proposed computation-controllable algorithm makes it easy to be integrated into the coding system(More)
Image pipeline processing is crucial to generating high quality images in applications using complementary metaloxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and(More)
Global motion estimation (GME) and compensation is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). However, there are no hardware architectures for GME since existing algorithms are not suitable for hardware implementation. In this paper. GME in MPEG-4 ASP is analyzed, and a hardwareoriented GME algorithm is proposed according to the(More)
This paper presents an LSI design for MPEG-4 video coding. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A fast motion estimator architecture supporting predictive diamond search and spiral full search with halfway termination is implemented to make good compromise between compression performance and(More)