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A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional(More)
This paper deals with the diagnosis of eld pro-grammable interconnect systems (FPIS) in which nets are c onnected through programmable switches arranged in grids. A hierarchical approach to diagnosis is proposed. The conditions by which such process yields full diagnosis and the characteristics of the programming sequence, are fully proved. For a FPIS(More)
This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint(More)