Wei-Kai Cheng

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We propose a method for compiling an application program into microcode of a programmable DSP processor. Since most state-of-the-art DSP processors feature some sort of parallel processing architectures, the code generation is a non-trivial task. Based on several scheduling and allocation techniques previously developed by the CAD community for high-level(More)
Since most DSP applications access large amount of data stored in the memory, a DSP code generator must minimize the addressing overhead. In this paper, we propose a method for addressing optimization in loop execution targeted toward DSP processors with auto-increment/decrement feature in their address generation unit. Our optimization methods include a(More)
We propose a microcode-optimizing method targeting a programmable DSP processor. Efficient generation of microcodes is essential to better utilize the computation power of a DSP processor. Since most state-of-the-art DSP processors feature some sort of irregular architectures and most DSP applications have nested loop constructs, their code generation is a(More)
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-specific integrated circuits (ASICs) and application-specific instruction-set processor (ASIPs) have been frequently designed using the HLS approach. Since most ASIP and DSP processors provide multiple addressing modes, and, in(More)
Three dimensional integrated circuits allow multiple devices to be stacked on multiple layers. Therefore, utilize the area of each layer efficiently and minimize the number of through silicon vias (TSVs) are crucial to the 3D IC design. In this paper, we propose an integer linear programming (ILP) model to perform simultaneous resource binding and layer(More)