Wei-Chieh Yu

Learn More
In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that(More)
In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that(More)
Retiming transformation relocates registers in a circuit to shorten the clock cycle time. However, with the advent of deep sub-micron era, the hold constraints often limit the smallest feasible clock period that the retiming transformation can achieve. Therefore, a combination of retiming transformation and delay insertion may lead to further clock period(More)
  • 1