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A DCO is realized in 0.13µ CMOS using 4 cores for a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for an all digital D/PLL CDR circuit. The DCO is novel in that it can track more than a 130 degree C temperature variation while the CDR maintains an error free lock to data. Each core is directly coupled to a div/2 to produce I/Q signals(More)
A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13&#x03BC;m CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exceeds all SONET jitter specifications from OC-3 to OC-192, with random jitter of 452fs at 9.95Gb/s. The die area is 2&#x00D7;2mm<sup>2</sup>, and is implemented in a 24-pin LFCSP.
A 12.5 Gb/s half-rate clock and data recovery (CDR) circuit is described. The CDR uses a half-rate linear phase detector (LPD) which minimizes the number of latches required. To correct for static phase offsets (SPO) that inevitably result from variations in analog circuit parameters, a calibration scheme is used on startup. Measured high-frequency jitter(More)
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