Learn More
This paper first presents the architecture of a frequency synthesizer which can support multi-standard wireless systems of GPS, Galileo, and WCDMA standards. Then, a programmable integer/fractional combined frequency divider (CFD), which is the key building block of the proposed frequency synthesizer, is designed and implemented by using 0.18μm RF CMOS(More)
In this paper, we report a limiting amplifier (LA) for optical access networks (OAN) and gigabit Ethernet (GbE). Active inductors are employed as loads to expand the bandwidth and to get stable DC operating points. Omitting source followers (SK); the modified direct-coupled technique is used to reduce power dissipation. This LA exhibits an input dynamic(More)
A low jitter 1 GHz phase locked loop (PLL) circuit for clock synchronization of high-speed data transmission systems has been realized monolithically in a native 0.6/spl mu/m CMOS technology. The implemented PLL consists of a phase detector (PD), a loop filter and a three-stage voltage-controlled ring oscillator (ring VCO). Fully differential topology is(More)
The channel bridging, signal regenerating, and functional rebuilding of injured nerves is one of the most important issues in life science research. In recent years, some progresses in the research area have been made in repairing injured nerves with microelectronic neural bridge. Based on the previous work, this paper presents a neural signal detection and(More)
This paper presents an ultra-high-speed comparator for ADC (analog to digital converter) which could be used in SWR (software radio). In this design, based on 0.35-μm SiGe BiCMOS process, a small size MOSFET is used to take place of the current bias and the control switch in the traditional HBT comparator, thus it could make the comparator faster(More)
A behavior model for the communication link of Ethernet Passive Optical Network (EPON) is presented. It consists of a fiber, a photodiode, a transimpedance amplifier (TIA) followed by a limiting amplifier and a clock and data recovery (CDR) circuit. Each part of the model is based on the architecture of its circuit to improve the model accuracy. The noise(More)
A Device to detect for the bladder which is full with urine is designed. The device can measure bladder pressure. The pressure signals are processed. When the pressure exceeds 40cm water column, Pressure signal exceeds a fixed voltage. At the same time, Oscillator sends a signal and the signal transmits to the body surface. The receiver accepts the(More)
In this paper, a Broadband LC Voltage Controlled Oscillator (VCO) with low phase noise for wireless communications is realized by a 0.18-μm CMOS process. In order to optimize the turning curve, reduce the phase noise, and increase the linearity, a cross-coupled LC structure is selected. At the same time, a capacitor working in accumulation area and(More)
As one of the basic concepts of the Chinese medicine, the theory of Meridians and Collaterals is lack of scientific demonstration so far. In order to verify the existence of Meridians and Collaterals, a method based on the electric technique and information theory is suggested, A specialized electrode array has been designed and an experimental scheme of(More)
  • 1