Wang Xing-hua

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A pipelined ADC using shared amplifiers in two-channel time-interleaved design is proposed. The two channels have a unify sample and hold amplifier. In the time-interleaved pipelined part, the large mismatch between the channels is reduced by the shared amplifier in the same stage. And power consumption and chip area also been decreased. Under SMIC 0.35um(More)
A kind of behavior model for discrete sampling and hold amplifier with charge transmission is analyzed. The transfer function and behavior features are based on the main AC responses of operation amplifier. The result used in pipelined and sigma-delta ADC shows the exact of model of sampling and hold amplifier, and the non-ideal factors are taken into(More)
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