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A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control
  • M. Choi, Sung-No Lee, +4 authors H. Lee
  • Physics, Computer Science
  • IEEE Custom Integrated Circuits Conference
  • 17 November 2008
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. Expand
  • 26
  • 1
A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure
A 2.7V 4mW per-channel 20-bit 48kS/s sigma-delta stereo audio DAC, integrated in a 0.13mum CMOS technology, achieves a dynamic range (DR) of 101dB and occupies an active die area of 0.82mm2. Expand
  • 7
  • 1
A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS
The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Expand
  • 6
A self-calibration 103-dB SNR stereo audio DAC with true-GND class-D headphone drivers in 45nm CMOS
A stereo audio DAC with ground-centered class-D headphone drivers is fully integrated in a 45nm CMOS technology. Expand
A 2.4 V, 12 mW stereo audio D/A converter with double sampling switching
A 2.4 V 16-bit stereo audio digital-to-analog (D/A) converter was implemented using a 0.35 /spl mu/m CMOS technology. Expand
  • 1
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Three-level PWM amplifiers and audio processing apparatus
The invention relates to a three-level pulse width modulation (PWM) amplifier and audio processing apparatus including the same. Expand