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1 September 2008
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. A post integration time… Continue Reading
1 September 2006
A 2.7V 4mW per-channel 20-bit 48kS/s sigma-delta stereo audio DAC, integrated in a 0.13mum CMOS technology, achieves a dynamic range (DR) of 101dB and occupies an active die area of 0.82mm2. The… Continue Reading
1 June 2008
The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Novel asymmetric pulse-width modulation (PWM) is applied to… Continue Reading
1 November 2010
A stereo audio DAC with ground-centered class-D headphone drivers is fully integrated in a 45nm CMOS technology. A built-in self-calibration is proposed to minimize DC offset voltage causing static… Continue Reading
IEEE International Symposium on Circuits and…
A 2.4 V 16-bit stereo audio digital-to-analog (D/A) converter was implemented using a 0.35 /spl mu/m CMOS technology. The DAC utilize an interpolation filter, 1-bit 4th-order noise shaper,… Continue Reading
14 September 2010
1. Three-level PWM amplifiers and audio processing apparatus. 2.1. The invention relates to a three-level pulse width modulation (PWM) amplifier and to an audio processing apparatus including the… Continue Reading