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A scheme of ultra-long variable-size pipelined FFT processor is presented and a prototype is implemented with one FPGA, which may compute various 4<sup>n</sup> (n = 1 ~ 10) points FFT at a speed as high as 150 MHz. The solutions are to transform the one-dimension FFT to two-dimension repeatedly, and propose an efficient twiddle-factor memory compression(More)
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