Walter Godoy

Learn More
This paper presents a new hardware implementation for boolean matrix inverters. A circuit capable of inverting a nonsingular N×N matrix in exactly N clock cycles is introduced, described, and tested in FPGA devices. This is an improvement over the fastest implementation reported to date, which computes the inverted matrix in 2N clock cycles on average(More)
The objective of this paper is to analyze the bound of addition proposed by Barros et al. (Computer Communication 20(4) (1997) 302–308) in contrast to the GMD bound (Forney, IEEE Trans. Inf. Theory IT-12 (1996)) and the cone bound (Godoy, Doctoral Thesis, UNICAMP, Campinas, SP, Brazil, 1990) which shows the Voronoi region of the zero code-word for a(More)
The objective of this paper is twofold: firstly it aims at analyzing two acceptance criterions independently proposed by Taipale and Pursley (in 1989) and by Barros, Godoy and Wille (in 1993); and secondly to present the Real-Time Modified Information Set (RT-ISA) soft-decision decoding algorithm for block codes that is based on the BGW criterion. The(More)
The most important desidered characteristic for today's networks is quality of service (QoS). Currently DiffServ-based MPLS networks are able to the development of efficient methods for QoS provisioning. This article analysis, through computer simulation, the performance of WFQ schedulers in a DiffServ node loaded by long range dependence (LRD) traffic. The(More)