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- Gregory F. Pfister, William C. Brantley, +6 authors Jodi Weiss
- ICPP
- 1985

- William C. Brantley, David A. George, +5 authors Shreekant S. Thakkar
- 1993

Memory contention can be a major source of overhead in large-scale shared-memory multiprocessors. Although there are many hardware solutions to the problem of memory contention, these solutions are often complex and expensive, so software solutions are an attractive alternative. This paper evaluates one particular software solution, called block-column… (More)

- Bruce M. Maggs, William C. Brantley, David A. George, Steve L. Harvey, Wally J. Kleinfelder, K. P. McAuli
- 2011

It follows from Equations 7 and 8 that the number of nodes in cut N(A) is at least (1 + o(1))k 1 2blogkc = (1=2 + o(1)) k log k

- C . Bouras, P . G . Spirakis, +5 authors Victor Norton
- 2007

Note that (26) proves Theorem 6 for b = 1. For b < 1, the situation for p b has to be given special consideration: Pr(q (n) In steady state we get By the same way, working inductively, one may show that for k j < b we get : p j x k;0 = p j?k+1 x k;k + p j?k+2 (x k;k+1 + x k;k) + + p j?1 (x k;2 + + x k;k); thus proving Theorem 6 , for b < 1 (including the… (More)

- George B. Adams, Dharma P. Agrawal, +6 authors Wally J. Kleinfelder
- 2004

The Realizer is a logic emulation system that automatically configures a network of Field-Programmble Gate Arrays (FPGA’s) to implement large digital logic designs. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing… (More)

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