Wagner Penny

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Preliminary results from real-time ‘brain-computer interface’ experiments are presented. The analysis is based on autoregressive modelling of a single EEG channel coupled with classification and temporal smoothing under a Bayesian paradigm. It is shown that uncertainty in decisions is taken into account under such a formalism and that this may be used to(More)
We present an overview of our research into brain-computer interfacing (BCI). This comprises an offline study of the effect of motor imagery on EEG and an online study that uses pattern classifiers incorporating parameter uncertainty and temporal information to discriminate between different cognitive tasks in real-time.
This paper presents a high throughput architecture for a Motion Compensation (MC) sample interpolator targeting the High Efficiency Video Coding (HEVC) standard. Real-time operation and low power dissipation in video coding systems have become important research challenges, especially in mobile devices with limited computational resources and battery(More)
This paper presents an empirical assessment of the Bayesian evidence framework for neural networks using four synthetic and four realworld classification problems. We focus on three issues; model selection, automatic relevance determination (ARD) and the use of committees. Model selection using the evidence criterion is only tenable if the number of(More)
The current state-of-art video coding standard, the High Efficiency Video Coding (HEVC), brings many innovations as a way to improve the coding performance. However, the improvement on performance also brought higher computational effort and energy consumption. Since most of devices that handle digital videos are battery powered, the energy consumption(More)
Brain Computer Interface (BCI) is an emerging research area which tries to capture the motor imagery thought process from brain using Electro-encephalogram (EEG) and process the data using signal processing techniques to classify the motor imagery thought process. Physically impaired people without any muscular activity can carry on their day to day(More)
This paper presents a hardware design for the sub-sample interpolator used in FME (Fractional Motion Estimation) and MC (Motion Compensation) stages according to the VP9 and VP10 video-coding standards. The proposed architecture is able to save hardware resources through an optimized-filter organization whereas reaching high-throughput and low-power(More)
Real-time operation and low-power dissipation in video coding systems have become important research challenges, especially in mobile devices with limited battery and computational resources. There are many video coding standards coexisting in the market nowadays, so it is important for current devices to support different video coding standards. This paper(More)
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