• Publications
  • Influence
Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates
TLDR
An EDA tool is introduced that quickly and accurately estimates the reliability of any CMOS gate by taking into consideration the gate's topology,the reliability of the individual devices, the applied input vector, as well as the noise margins. Expand
A Web-Based Course Assessment Tool with Direct Mapping to Student Outcomes
TLDR
A methodical approach as well as a Web-based automation of the assessment process, which is evaluated in the context of the regular academic assessment cycles that have eventually led to a successful international accreditation experience. Expand
Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates
  • W. Ibrahim
  • Computer Science
  • IEEE Transactions on Computers
  • 1 June 2016
TLDR
A progressive consensus-based algorithm for identifying the worst reliability input vectors and the associated critical logic gates that scales well with circuit size, and is independent of the interconnect complexity and the logic depth. Expand
On the Reliability of Majority Gates Full Adders
This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that of a standard XOR-based FA. The analysis provides insights into differentExpand
Improving solver success in reaching feasibility for sets of nonlinear constraints
TLDR
A range of computationally cheap constraint consensus algorithms that move from a given initial point to a better final point that is then passed to the nonlinear solver, and a new initial point placement heuristic for use when an initial point is not provided by the modeller. Expand
Accurate and Efficient Estimation of Logic Circuits Reliability Bounds
TLDR
This paper presents a complete solution for estimating logic circuit reliability bounds with high accuracy in reasonable time, even for very large and complex circuits, and is independent of the interconnect complexity or the logic depth. Expand
Enabling sizing for enhancing the static noise margins
TLDR
Simulation results show that this sizing method enables more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence leading to ultra-low voltage/power circuits. Expand
Does the brain really outperform Rent’s rule?
TLDR
It is concluded that, among quite a few network topologies, the crossbar (for very small sizes) and the cube connected cycles are highly competitive contenders for future brain-inspired nanoarchitectures. Expand
PerfPred: A web‐based tool for exploring computer architecture design space
TLDR
This paper presents a Web‐based tool for predicting the performance of computer systems that can be used for teaching how the hardware configurations and software characteristics can affect the system throughput. Expand
Critical nodes count algorithm for accurate input vectors reliability ranking
TLDR
An accurate reconvergent-based algorithm for input vector reliability ranking that significantly reduces the complexity of identifying the worst reliability input vector is introduced and Simulation results show that proposed algorithm is efficient and more accurate than any other ranking algorithms currently proposed in the literature. Expand
...
1
2
3
4
5
...