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The interface message processor for the ARPA computer network
TLDR
The ARPA Network will initially interconnect many dissimilar computers at ten ARPA-supported research centers with 50-kilobit common-carrier circuits, but the network may be extended to include many other locations and circuits of higher bandwidth.
The Data Transfer Protocol
The terminal IMP for the ARPA computer network
TLDR
A little over three years ago the Advanced Research Projects Agency began implementation of an entirely new venture in computer communications: a network that would allow for the interconnection, via common-carrier circuits, of dissimilar computers at widely separated, ARPA-sponsored research centers.
The Monarch parallel processor hardware design
TLDR
The Monarch architecture team took advantage of custom VLSI in the design of a shared-memory parallel processor that eases the task of programming a massively parallel machine.
Improvements in the design and performance of the ARPA network
In late 1968 the Advanced Research Projects Agency of the Department of Defense (ARPA) embarked on the implementation of a new type of computer network which would interconnect, via common-carrier
Issues in packet switching network design
TLDR
Several of the key design choices that must be made in specifying a packetswitching network are identified and some insight is provided in each area.
A new minicomputer/multiprocessor for the ARPA network
Since the early years of the digital computer era, there has been a continuing attempt to gain processing power by organizing hardware processors so as to achieve some form of parallel operation. One
Flow Control in a Resource-Sharing Computer Network
TLDR
This paper examines in some detail the nature of the flow control required in the subnet and its relation to the host flow control and subnet performance.
Pluribus: a reliable multiprocessor
TLDR
As computer technology has evolved, system architects have continually sought new ways to exploit the decreasing costs of system components to gain increased operating power through parallelism and/or to gain increases in system reliability through redundancy.
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