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3D die-stacking (Tanida et al, 2003; Hara et al, 2005) and wafer-stacking (Morrow et al, 2004) integration have recently been demonstrated using copper (Cu) interconnections and through silicon via technology. In 3D die-stacking approach, the Cu vertical interconnections are fabricated on the front-side of the silicon wafer along with the active circuitry(More)
Reduction in inter-level dielectric (ILD) constant has been accompanied by a reduction in ILD adhesive and cohesive strength thus increasing potential for under bump (flip-chip) ILD cracking during packaging and reliability testing. Two primary mechanisms were determined to cause this failure: (1) stress on the ILD created due to the coefficient of thermal(More)
This paper describes the development of deep via plating in silicon substrates. Straight walled and tapered vias were plated through photoresist openings usually with bumps plated on top of via. In the second section similar vias were completely or partly filled, in process called "barrel" plating, in the absence of photoresist. The latter process turned(More)
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