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We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise(More)
The TOTEM collaboration has measured the proton-proton total cross section at √s=8 TeV using a luminosity-independent method. In LHC fills with dedicated beam optics, the Roman pots have been inserted very close to the beam allowing the detection of ~90% of the nuclear elastic scattering events. Simultaneously the inelastic scattering rate has been measured(More)
The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal(More)
The TOTEM collaboration has developed and tested the first prototype of its Roman Pots to be operated in the LHC. TOTEM Roman Pots contain stacks of silicon detectors with strips oriented in two orthogonal directions. To measure proton scattering angles of a few microradians, the detectors will approach the beam centre to a distance of 10σ + 0.5 mm (=(More)
The features of the 180nm TowerJazz<sup>1</sup> CMOS technology allow for the first time the use of CMOS Monolithic Active Pixel Sensors (MAPS) under the harsh operational conditions of the LHC experiments. The stringent requirements of the ALICE Inner Tracking System (ITS) in terms of material budget, radiation hardness, readout speed and a low power(More)
  • W. Snoeys
  • ESSCIRC 2014 - 40th European Solid State Circuits…
  • 2014
Integrated circuits and devices revolutionized particle physics experiments, and have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider at CERN. Particles are accelerated and brought into collision at specific interaction points. Detectors are giant cameras, about 40 m long by 20 m in(More)
The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal(More)