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A new fault model is developed for estimation of the coverage of physical defects by hierarchical defect simulation. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the conditional defect probabilities. A description and the experimental data… (More)
In the paper transmission line pulsing (TLP) methodology and testers are described. In contrast to commonly available publications, which usually lack information on testers' design, the authors describe TLP tester's construction details. This includes an applied electric diagram. Conclusions based on up-to-date research and preliminary test results… (More)
This paper describes the analysis of influence of yield loss model parameters on the test patterns generation. The probability of shorts between conducting paths as well as the estimations of yield loss are presented on the example gates from industrial standard cell library in 0.8 mum CMOS technology.
In this paper local clock signal generator basing on three different ring oscillators is discussed. The structure was designed to verify possibility of local clock signal generation using basic delay stages. General simulations were performed to analyze power dissipation and stability of frequency in regard to temperature, transistor model and layout… (More)
A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defectJault relationships in the form of defect… (More)