W. Paul Griffin

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In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with(More)
This is to certify that the thesis/dissertation prepared By Entitled For the degree of Is approved by the final examining committee: Chair To the best of my knowledge and as understood by the student in the Research Integrity and Copyright Disclaimer (Graduate School Form 20), this thesis/dissertation adheres to the provisions of Purdue University's "(More)
Proper understanding of the effects of parameter variations in a circuit requires simulation; unfortunately, accurate variation simulation can hinder simulation performance. Even though the majority of interdie variations occur between four parameters (L, W, t<sub>ox</sub>, V<sub>fb</sub>) [1], this parameter set is still too big for efficient large-scale(More)
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