W. Jeamsaksiri

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This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the(More)
Analog/RF CMOS design in deep-sub micron digital CMOS is particularly challenging due to conflicting device performance requirements. The continuous scaling of digital CMOS has resulted in cut-off frequencies (f/sub T/) above 100Hz. however this improvement comes at a cost of degraded output resistance and reduced intrinsic gain. The difficulty of(More)
A novel low-power 90 nm CMOS 5.8 GHz voltage-controlled oscillator, using a high quality thin-film post-processed inductor, is presented. This 5.8 GHz VCO has a power consumption of 328 /spl mu/W with a supply voltage of 0.82 V, and a phase noise of -115 dBc/Hz at 1 MHz offset over a 148 MHz tuning range. To the authors' knowledge, this VCO is the lowest(More)
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