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In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process(More)
Hardware implementation of triadic fault-free simulation method HES-MV - hardware embedded simulation based on multi-valued alphabet is proposed. This method uses hardware gate and RTL models for large scale digital designs description. Structure solutions for logic elements models implementation are presented. Logic element has two bits for four values(More)
The paper presents the architecture and implementation of lifting-based wavelet transform for 5/3 filter bank of JPEG2000 standard is presented. The architecture has regular data flow and low control complexity. RTL-level hardware description language model was designed. Device speed analysis for different chip series of Xilinx FPGA was realized.
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