Vyas Venkataraman

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— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a lack of design tools make this requirement very difficult to satisfy in practice. We present a novel asynchronous dual-rail gate design which is power balanced and capable of tolerating(More)
Cryptographic hardware is vulnerable to power analysis attacks. To resist these attacks, special balanced dual-rail gates have been developed which have equal power consumption for all valid data values and transitions. A limitation of existing designs is that they require balanced routing of the dual-rail interconnect between gates. Natural process(More)
Transaction-level modeling is an essential component of system-level design. This paper advocates using rendezvous, a construct common to concurrent programming languages, as a theoretical foundation for transactions. Compared to regular function calls, rendezvous are atomic and support multipartiness and parallel composition. However, scheduling multiparty(More)
Due to the large semantic gap between transaction level models and actual implementations, hardware synthesis based on system level models has been a great challenge. Aiming to close the semantic gap, we studied an approach that uses rendezvous to model communication. By allowing both conjunctive and disjunctive composition of rendezvous, the approach(More)
As the complexity of modern systems grow, the level of abstraction of their descriptions must similarly increase, as evidenced by the growing shift towards Transaction Level Modeling (TLM). While these methodologies are useful in abstracting the complexity of the computation, their lack of a formal foundation for representing concurrency makes the modeling(More)
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