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—High-level synthesis is comprised of interdependent tasks such as scheduling, allocation, and module selection. For today's very large-scale integration (VLSI) designs, the cost of solving the combined scheduling, allocation, and module selection problem by exhaustive search is prohibitive. However, to meet design objectives, an extensive design space(More)
A new C-seco tetranortriterpenoid named as 6-homodesacetylnimbin 2, has been synthesised for the first time through semi-synthetic modification of nimbolide 1, a potent molecule with anticancer activity. Attempts were made to transesterify the -COOMe moiety in nimbolide using titanium (IV) isopropoxide and ethanol so as to obtain a molecule with -COOEt(More)
We present an assessment of a priori stochastic wirelength estimation as a viable technique for evaluating the interconnect requirements of designs explored in RTL datapath synthesis. The model estimates the wirelength requirements of a gate level netlist a priori, based on Rentian parameters extracted dynamically from RTL netlists. Experimental results(More)
Autospec was designed to acquire data output from a Beckman DU series 60 spectrophotometer and to process these data with an IBM or IBM-compatible computer. It functions in conjunction with the Beckman DU Data Capture and Lotus 1-2-3 softwares. Autospec automatically stores data produced by the spectrophotometer, determines standard curves and calculates(More)
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