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- Victor Varshavsky, Vyacheslav Marakhovsky, V. A. Peschansky
- Mathematical systems theory
- 1970

The problem of synchronizing an automata chain, as posed by J. Myhill [1,2,3,4,5] provides us with a number of models which seem to be meaningful. We modify the statement of the problem as follows. Does there exist a finite automaton A such that a chain of n automata A would be synchronized at time t = T after being "switched on" at time t = 0 by an… (More)

- Victor Varshavsky, Vyacheslav Marakhovsky
- Application and Theory of Petri Nets
- 1996

- Victor Varshavsky, Vyacheslav Marakhovsky
- IWANN
- 1999

- Victor Varshavsky, Vyacheslav Marakhovsky
- Concurrency and Hardware Design
- 2002

The problem of organizing the temporal behavior of digital systems is discussed. This problem is mainly associated with providing the interface between physical (natural) and logical (artificial) time. The most common method of interfacing is based on a system clock that removes physical time from the behavior models A number of algorithms that can be… (More)

- Victor Varshavsky, Vyacheslav Marakhovsky
- Fuzzy Days
- 1999

A functional completeness of summing amplifier with saturation in a multi-valued logic of an arbitrary value proven in previous works gives a theoretical background for analog implementation of fuzzy devices. Practical design techniques for multi-valued analog fuzzy controllers still have to be developed. Compared with the traditional approach, analog CMOS… (More)

- Victor Varshavsky, Vyacheslav Marakhovsky
- DELTA
- 2002

- Victor Varshavsky, Vyacheslav Marakhovsky, Vadim V. Smolensky
- IEEE Design & Test of Computers
- 1995

&YNCHRONOUS SYSTEMS offer many advantages in terms of performance and power. Designing them, however, is essentially an art (see the Designers as artists box), and the quality of the final circuit implementation depends greatly on the designer’s skill. Our research, therefore, defines a procedure that reliably accomplishes the routine work associated with… (More)

In the traditional dual-rail signalling, setting and resetting (after a suitable delay or after completion detection) wire x0 (resp. x1) indicates binary 0 (resp. 1). For example, for a sequence of values 001, the corresponding signal transition trace will be x0+(valid 0), x0(spacer), x0+ (valid 0), x0-(spacer), x1+ (valid 1), x1(spacer). Here, the number… (More)