If you want to get CIRCUIT DESIGN AND SIMULATION WITH VHDL, 2/e pdf eBook copy write by good author PEDRONI, VOLNEI A., you can download the book copy here. The CIRCUIT DESIGN AND SIMULATION WITH VHDL, 2/e we think have quite excellent writing style that make it easy to comprehend. ????. This text offers a comprehensive treatment of VHDL and its… (More)
We present an analog VLSI chip for parallel analog vector quantiza-tion. The MOSIS 2.0 J..Lm double-poly CMOS Tiny chip contains an array of 16 x 16 charge-based distance estimation cells, implementing a mean absolute difference (MAD) metric operating on a 16-input analog vector field and 16 analog template vectors. The distance cell including dynamic… (More)
—We present a parallel analog vector quantizer (VQ) in 2.0-m double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16 2 16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic… (More)
McEliece and Lin introduced the minimal trellis for convolutional codes, which can be considerably less complex than the conventional trellis typically used to construct Viterbi decoders. The authors state that this reduced trellis complexity can lead to less complex Viterbi decoders in practice. In this paper, we compare conventional and minimal Viterbi… (More)
Below are some of the VHDL codes from the examples in Part II of the book (Chapters 19-25).
This paper describes the implementation of a sigma-delta () A/D converter within an FPGA, with minimal use of external analog components. The approach takes advantage of existing low-voltage differential signaling (LVDS) I/O pads; this allows the implementation of low-cost ADCs into existent FPGAs, even though such digital devices do not posses analog… (More)
This paper presents a new hardware implementation for boolean matrix inverters. A circuit capable of inverting a nonsingular N×N matrix in exactly N clock cycles is introduced, described, and tested in FPGA devices. This is an improvement over the fastest implementation reported to date, which computes the inverted matrix in 2N clock cycles on average… (More)