Volnei A. Pedroni

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This paper presents a new hardware implementation for boolean matrix inverters. A circuit capable of inverting a nonsingular N×N matrix in exactly N clock cycles is introduced, described, and tested in FPGA devices. This is an improvement over the fastest implementation reported to date, which computes the inverted matrix in 2N clock cycles on average(More)
This paper describes the implementation of a sigma-delta ( ) A/D converter within an FPGA, with minimal use of external analog components. The approach takes advantage of existing low-voltage differential signaling (LVDS) I/O pads; this allows the implementation of lowcost ADCs into existent FPGAs, even though such digital devices do not posses analog(More)
We present a parallel analog vector quantizer (VQ) in 2.0m double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16 16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic(More)
McEliece and Lin introduced the minimal trellis for convolutional codes, which can be considerably less complex than the conventional trellis typically used to construct Viterbi decoders. The authors state that this reduced trellis complexity can lead to less complex Viterbi decoders in practice. In this paper, we compare conventional and minimal Viterbi(More)
Software-based network security is constantly challenged by the increase in network speeds and number of attacks. At the same time, mobile network access underscores the need for energy efficiency. In this paper, we present a new way to improve the throughput and to reduce the energy consumption of an anomaly-based intrusion detection system for probing(More)