Volnei A. Pedroni

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This paper presents a new hardware implementation for boolean matrix inverters. A circuit capable of inverting a nonsingular N×N matrix in exactly N clock cycles is introduced, described, and tested in FPGA devices. This is an improvement over the fastest implementation reported to date, which computes the inverted matrix in 2N clock cycles on average(More)
McEliece and Lin introduced the minimal trellis for convolutional codes, which can be considerably less complex than the conventional trellis typically used to construct Viterbi decoders. The authors state that this reduced trellis complexity can lead to less complex Viterbi decoders in practice. In this paper, we compare conventional and minimal Viterbi(More)
This paper describes the implementation of a sigma-delta () A/D converter within an FPGA, with minimal use of external analog components. The approach takes advantage of existing low-voltage differential signaling (LVDS) I/O pads; this allows the implementation of low-cost ADCs into existent FPGAs, even though such digital devices do not posses analog(More)