Volkan Kursun

Learn More
Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed techniques to reduce leakage in on-chip storage structures. In this study, static energy is reduced in the integer functional units by leveraging the unique(More)
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today’s high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage(More)
— The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of(More)
An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive(More)
An analysis of the power characteristics of a buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A parasitic model of the buck converter is developed. With this model, a design space is determined that allows integration of active and(More)
A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc–dc converters. The parasitic power dissipation of a dc–dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a(More)
Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe shortchannel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this(More)