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Parameter variations cause high yield losses due to their large impact on circuit delay. In this paper, we propose the use of so-called soft-edge flip-flops as an effective way to mitigate these yield losses. Soft-edge flip-flops have a small window of transparency (ranging from 0.25-3 FO4) instead of a hard edge, allowing limited cycle stealing on critical(More)
In this paper, we present a new flipflop sizing scheme that efficiently immunizes combinational logic circuits from the effects of radiation induced single event transients (SET). The proposed technique leverages the effect of temporal masking by selectively increasing the length of the latching windows associated with the flipflops thereby preventing(More)
Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current CMOS technologies. In this paper, we study how stress-induced performance enhancements are affected by layout properties and suggest guidelines for improving layouts so that performance gains are maximized. All MOS devices in this work include(More)
In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as <i>t</i><sub><i>ox</i></sub>, <i>V</i><sub><i>th</i></sub>, and(More)
Soft errors in combinational logic circuits are emerging as a significant reliability problem for VLSI designs. Technology scaling trends indicate that the soft error rates (SER) of logic circuits will be dominant factor for future technology generations. SER mitigation in logic can be accomplished by optimizing either the gates inside a logic block or the(More)
Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobility which, consequently, increases both <i>I</i><sub><i>on</i></sub> and <i>I</i><sub><i>off</i></sub>(More)
Suppresing device leakage while maximizing drive current is the prime focus of semiconductor industry. Rapid Thermal Annealing (RTA) drives process development on this front by enabling fabrication steps such as shallow juction formation that require a low thermal budget. However, decrease in junction anneal time for more aggresive device scaling has(More)
Picture archiving and communication systems (PACS) are being widely adopted in radiology practice. The objective of this study was to find radiologists' perspective on the relative importance of the required features when selecting or developing a PACS. Important features for PACS were identified based on the literature and consultation/interviews with(More)
—Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current CMOS technologies. This paper explores how to fully exploit the layout dependency of stress enhancement and proposes a circuit-level, block-based, stress-enhanced optimization algorithm that uses stress-optimized layouts in conjunction with(More)