Vivek Chickermane

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The effectiveness of on-product Test Compression methods is degraded by the capture of unknown logic states (“X-states”) by the scan elements. This paper describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various(More)
IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper(More)
Recent studies show that a stuck-at test applied at the operational speed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. In this work, we investigate various design-for-testability (DFT) techniques for sequential circuits which permit at-speed application of tests while providing for(More)
This paper describes an Economic and Return-onInvestment (RoI) model for a test methodology that ensures product quality for logic devices that are in the 130 nm technology node and below. We describe the key components of the nanometer test methodology (NTM) and how it drives the model. In addition to ensuring product quality we address the cost of test(More)
Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-fortestability approaches based on full scan, partial scan or silicon-based solutions such as Cnwscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the(More)