Visvesh S. Sathe

Learn More
AMD’s 32-nm x86-64 core code-named “Piledriver” features a resonant global clock distribution to reduce clock distribution power while maintaining a low clock skew. To support a wide range of operating frequencies expected of the core, the global clock system operates in two modes: a resonant-clock (rclk) mode for energy-efficient operation over a desired(More)
In this paper, we present the design and experimental validation of RF1, a 0.8-1.2GHz frequency-scalable, resonant-clocked FIR filter test-chip with level-sensitive latches. Designed using a fully automated ASIC flow, RF1 was fabricated in a 0.13mum CMOS process with an on-chip inductor and clock generator. At its resonant frequency of 1.03GHz, RF1(More)
Study on frequency distribution of serum inhibin levels--a peptide hormone involved in suppression of follicle stimulating hormone--was carried out using a specific radioimmunoassay developed in this laboratory, on 237 sera from normal men and women, from male and female patients with cancer prostate, lung, stomach and breast, and from patients with(More)
This paper presents a finite impulse response (FIR) filter chip that relies on a charge-recovery logic family to achieve multi-MHz clock frequencies with subthreshold DC supply levels. Fabricated in a 0.13 m CMOS process with , the FIR operates with a two-phase power-clock in the 5 MHz–187 MHz range and with DC supplies in the 0.16 V–0.36 V range. Using a(More)
In this paper, we propose boost logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery techniques to achieve high energy efficiency at frequencies in the GHz range. The key feature of our design is the use of an energy recovering "boost" stage to provide an efficient gate overdrive to a highly voltage-scaled logic at(More)
Many complex industrial processes are multivariable with multiple inputs and multiple outputs. Generally multivariable systems are characterized by complicated cross couplings where control loops sometimes interact and even fight against each other. This poses significant challenges in designing control systems for these processes. Thus interaction analysis(More)
In this paper, we present Boost Logic, a chargerecovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. In post-layout simulations of 16-bit multipliers with a 0.13m CMOS(More)
Atib~ ~ ~~~ ~~~~~~~~~~~~~~~~~d B1A CriicaPa1 In this paper we present the design and experinmental Vdd B-LAT CriticalPath .Simnrratiorn validation of RF2, a 1 GHz, two-phase resonant-clocked FIR H e C filter test-chip with a distributed resonant clock generator and c4 ll$M(2 t an on-chip inductor. RF2 is fabricated in a 0.13 qm CMOS G GG G GA process and(More)
We have recently designed, fabricated, and successfully tested an experimental chip that validates a novel method for reducing clock dissipation through energy recovery. Our approach includes a single-phase sinusoidal clock signal, an L-C resonant sinusoidal clock generator, and an energy recovering flip-flop. Our chip comprises a dual-mode ASIC with two(More)