Vishnu Ravinuthula

Learn More
In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost materials with losses in excess of 30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIFCEI25G, are specifying SerDes requirements for channels with 25dB loss at Nyquist and this has driven the development of SerDes with 4 or(More)
We describe a set of basic circuit building blocks for computation using an analog temporal step function representation for the inputs and outputs. Methods for computing weighted averages and thresholded differences are described. These techniques have advantages as CMOS process technologies scale since they minimize the analog circuitry required. We show(More)
We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <−65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and(More)
This paper presents a fully integrated, low power, low noise Phase-Locked Loop (PLL) implementing a temperature compensated class-C dual-core Voltage Controlled Oscillator (VCO) achieving state of the art phase noise performance. The PLL exhibits low integrated noise enabling the integration of low jitter clocks for high performance data converters(More)
  • 1