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In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost materials with losses in excess of 30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIF-CEI25G, are specifying SerDes requirements for channels with 25dB loss at Nyquist and this has driven the development of SerDes with 4(More)
This paper presents a fully integrated, low power, low noise Phase-Locked Loop (PLL) implementing a temperature compensated class-C dual-core Voltage Controlled Oscillator (VCO) achieving state of the art phase noise performance. The PLL exhibits low integrated noise enabling the integration of low jitter clocks for high performance data converters(More)
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