Vishal Vinayak Kulkarni

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Wearable technology is opening the door to future wellness and mobile experience. Following the first generation wearable devices in the form of headsets, shoes and fitness monitors, second generation devices such as smart glasses and watches are making an entrance to the market with a great potential to eventually replace the current mobile device platform(More)
High-speed optical module is demonstrated using silicon photonics integrated circuits (Si-PIC) by compact packaging on ceramic submount of which size is 4 mm x 21 mm x 1.1 mm. The electronic integrated circuits (EIC) such as transimpedance amplifier (TIA) for photodetector and driver IC for modulator are flip-chip bonded on the submount using 1 mil diameter(More)
Coexistence of various on-body and intra-body biomedical ICs call for the need of inter-device data communication at high speeds with ultra lower power consumption and smaller footprint. To address these needs, this work presents an injection locked clock and data recovery (CDR) circuit in 65 nm CMOS for body channel communication transceivers that employ(More)
With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power(More)
A low power, 5-Mb/s fully integrated body channel Frequency Shift Keying (FSK) transmitter using the human body as a signal transmission medium is designed for medical data transmission in body area network. The FSK transmitter has a 9-bit digitally controlled injection locked ring oscillator in place of the power consuming Phase-Locked Loop (PLL) to(More)
Body channel communication (BCC) integrated circuits for emerging wireless body area network multimedia applications call for the need of high-speed inter-device data communication at ultra-low-power consumption and smaller device footprint. In this paper, a novel low-power injection-locking-based clock-recovery circuit (CRC) is proposed for BCC(More)
This paper presents a self-resetting repeater based energy-efficient transceiver for a 28 nm 8×8 core NoC. The proposed transceiver operates error free up to a data rate of 5.1 Gb/s with an energy efficiency of 60.3 fJ/b/mm and latency of 98 ps/mm over 16 mm link with repeaters at every 1 mm. Owing to proposed circuit schemes including variable(More)
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