• Publications
  • Influence
Robust Boolean reasoning for equivalence checking and functional property verification
TLDR
We present a combination of techniques for Boolean reasoning based on BDDs, structural transformations, an SAT procedure, and random simulation natively working on a shared graph representation of the problem. Expand
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Circuit-based Boolean reasoning
TLDR
In this paper we present a combination of techniques for Boolean reasoning based on BDDs, structural transformations, and a SAT procedure natively working on a shared graph representation of the problem. Expand
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Equivalence checking combining a structural SAT-solver, BDDs, and simulation
TLDR
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches using a tight integration of a structural satisfiability solver, BDD sweeping, and random simulation. Expand
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Scalable Automated Verification via Expert-System Guided Transformations
TLDR
Transformation-based verification has been proposed to synergistically leverage various transformations to successively simplify and decompose large problems to ones which may be formally discharged. Expand
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Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system
TLDR
This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. Expand
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Automatic formal verification of fused-multiply-add FPUs
TLDR
In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPU). Expand
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Scalable Sequential Equivalence Checking across Arbitrary Design Transformations
TLDR
We discuss the role of SEC within IBM and present a diverse set of algorithms comprised within our SEC framework which we have found necessary for the automated solution of the most complex SEC problems. Expand
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Exploiting suspected redundancy without proving it
We present several improvements to general-purpose sequential redundancy removal. (1) We propose using a robust variety of synergistic transformation and verification algorithms to process theExpand
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Large-scale application of formal verification: From fiction to fact
  • Viresh Paruthi
  • Computer Science
  • Formal Methods in Computer Aided Design
  • 20 October 2010
TLDR
Formal verification has matured considerably as a verification discipline in the past couple of decades, becoming a mainstream technology in industrial design and verification methodologies and processes. Expand
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Automatic data path abstraction for verification of large scale designs
TLDR
We propose a simple methodology for abstracting away portions of the data path, thus rendering a large state-space model of the design amenable for verification using model checking. Expand
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