Vinoo Srinivasan

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This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Recon gurable Computing Systems) for automatically partitioning and synthesizing designs for recongurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speci cations at the behavior level, in the form of task(More)
This paper presents an integrated approach to hardware software partitioning and hardware design space exploration. We propose a genetic algorithm which performs hardware software partitioning on a task graph while simultaneously contemplating various design alternatives for tasks mapped to hardware. We primarily deal with data dominated designs typically(More)
This paper presents a novel technique to perform dynamic high-level exploration of a behavioral specification that is being partitioned for a multi-device architecture. The technique, unlike in traditional HLS, performs a global search on the four-dimensional design space formed by multiple partition segments of the behavior. Hence, the proposed technique(More)
This paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, facilitating its use across a variety of synthesis applications. We briefly discuss synthesis semantics of the USM representation and its use(More)
Packaging technology has tremendously improved over the last decade. Various packaging options such as ASICs, MCMs, boards, etc. should be well explored at early stages of the system-synthesis cycle. In this paper we present a hierarchical behavioral partitioning algorithm which partitions the input behavioral speci cation into a hierarchical structure and(More)
Multi-FPGA Architectures Vinoo Srinivasan Ranga Vemuri University of Cincinnati, Cincinnati OH 45221{0030. E-mail: fvsriniva, rangag@ececs.uc.edu Abstract This paper presents spade, a system for partitioning designs onto multi-fpga architectures. The input to spade is a task graph, that is composed of computational tasks, memory tasks and the communication(More)
A technique for designing self-checking logic for implementation in Xilinx FPGAs is proposed. Self-checking circuits can detect permanent and transient faults during normal operation. The technique uses two types of cells; a functional cell and a checker cell. The functional cell is composed of one CLB. If a fault occurs within a CLB , it produces identical(More)
This paper presents an integrated design system called sparcs (Synthesis and Partitioning for Adaptive Reconngurable Computing Systems) for automatically partitioning and synthesizing designs for recon-gurable boards with multiple eld-programmable devices (fpgas). The sparcs system accepts design speciications at the behavior level, in the form of task(More)