Vinod Pangracious

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3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communication is the 3D integration technology and the use of through-silicon vias (TSVs) for inter-layer(More)
A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multi-level network with the logic blocks placed at different Tree levels using Butterfly-Fat-Tree network topology. 2D physical layout(More)
An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration(More)
a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. HAL is a multidisciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or(More)
The semiconductor industry is reaching a fascinating confluence in several evolutionary trends that will likely lead to a number of revolutionary changes in the design, implementation, scaling, and the use of computer systems. However, recently Moore's law has come to a standstill since device scaling beyond 65 nm is not practical. 2D integration has(More)
—The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due the programming overhead of FPGA. Three-Dimensional (3D) integration is a promising technology to reduce wire lengths. Through Silicon Vias (TSV)(More)