Vinod K. Agarwal

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This paper is concerned with multiprocessor implementations of embedded applications specified as iterative dataflow programs, in which synchronization overhead tends to be significant. We develop techniques to alleviate this overhead by determining a minimal set of processor synchronizations that are essential for correct execution. Our study is based in(More)
This paper addresses the issues of printed circuit board (PCB) interconnect testing in the context of boundaryscan architecture. Boundary-scan architecture is treated here as the framework for a PCB level built-in self-test (BIST). A novel BIST method is developed which utilizes various features of the architecture. Boundary-scan architecture is shown to(More)
At is shown that one-dimensional, unilateral iterative logic ar-<lb>rays (1”s) of combinational cells are C-testable for multiple sequential<lb>faults, provided the fault-free cell functions satisfy appropriate conditions.<lb>The test sequence is of length 0((<lb>r 7 1 2 ~ 1 2 + 1 n n 3 ) .<lb>A ) , where n (resp. 1 1 1 )<lb>is the number of signal values(More)