- Full text PDF available (5)
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The… (More)
Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose… (More)
In this paper, a generic parametrizable VHDL description of a deflecting NoC switch is presented. In addition , a benchmark family of 8 switches representing different possible architecture configurations has been synthesized and tested. We have created a scalable testbench providing high-fault coverage test patterns for network implementations based on… (More)
Acknowledgements: We thank the TAs for their advice and Arun Chandrasekhar, author of  for many helpful comments and suggestions.
The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage… (More)