Vineeth Govind

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The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The(More)
The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage(More)
This paper aims at devising an optimized pseudorandom test methodology for NoCs and its architectural support. The guiding principle consists of using a test pattern compaction engine for generating minimal test lengths. We show the application of this principle driven by the objective to minimize test application time, at the cost of test wrapper(More)
In this paper, a generic parametrizable VHDL description of a deflecting NoC switch is presented. In addition, a benchmark family of 8 switches representing different possible architecture configurations has been synthesized and tested. We have created a scalable testbench providing high-fault coverage test patterns for network implementations based on this(More)
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