Vineet Agrawal

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Process monitors that independently sense on-die PMOS and NMOS as-fabricated performance are presented. The monitors provide digital outputs, making them easily integrated blocks on SOC designs. We present two monitor approaches, one primarily analog and one primarily digital, applied to both logic circuits and SRAM, which may require different optimal body(More)
— An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via V DD scaling and body biasing. Alternatively, DDC technology demonstrates 35% speed increase at(More)
An SoC with ARM&#x00AE; Cortex&#x2122;-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel&#x2122; (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via V<sub>DD</sub> scaling and body biasing. Alternatively DDC technology(More)
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