Learn More
We present novel and efficient methods for built-in self-test (BIST) of field-programmable gate arrays (FPGAs) for detection and diagnosis of permanent faults in current, as well as emerging, technologies that are expected to have high fault densities. Our basic BIST methods can be used in both online and offline testing scenarios, although we focus on the(More)
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1- and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE, and that avoid expensive adaptive diagnosis. To the best of(More)
Incremental physical CAD is encountered frequently in the so-calledengineering change order (ECO) process in which design changes aremade typically late in the design process in order to correctlogical and/or technological problems in the circuit. Incrementalrouting is a significant part of an incremental physical designmethodology. Typically after an ECO(More)
Cross Layer Awareness Optimization removes such boundaries allowing flow of information or communication between layers by allowing access among the layer for information exchange. The strict boundaries create dependency problem for the concerned layer as well as other layers. The prime question arises whether this attitude can be applied to wireless(More)
This paper emphasize on the Taylor's series expansion of sinusoidal, cosine, tangent and exponential functions. The strategy of these series is based on the Vedic mathematics. The impression of designing multiplier based series is embraced from the ancient Indian mathematics found in Wisdom Books `Vedas. Diverse constraints (static and dynamic power, noise(More)
We present novel and efficient methods for on-line testing and fault reconfiguration in FPGAs. The testing approach uses a ROving TEster (ROTE), which, while similar at a high level to a prior work, is significantly different in that the testing is much faster (thus reducing fault-detection latency) and has provable diagnosability. We present 1and(More)
  • 1