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We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1- and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE, and that avoid expensive adaptive diagnosis. To the best of(More)
Incremental physical CAD is encountered frequently in the so-calledengineering change order (ECO) process in which design changes aremade typically late in the design process in order to correctlogical and/or technological problems in the circuit. Incrementalrouting is a significant part of an incremental physical designmethodology. Typically after an ECO(More)
We propose a roving tester (ROTE) that tests the PLBs of the FPGA by periodically moving across it. At any time, the ROTE occupies a certain area of the FPGA, say two columns, and tests all PLBs in that area using parallel built-in self-tester (BISTers). A significant contribution of this work are designs for 1- and 2-diagnosable BISTers. To the best of our(More)
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