Vikram Iyengar

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Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more(More)
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and(More)
This paper presents the ITC’02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines the benchmark format and naming scheme, and presents the(More)
This paper describes an integrated framework for plug-and-play SOC test automation. This framework is based on a new approach for wrapper/TAM co optimization based on rectangle packing. We first tailor TAM widths to each core's test data needs. We then use rectangle packing to develop an integrated scheduling algorithm that incorporates precedence and power(More)
Test scheduling is a major problem in system-on-a-chip (SOC) test automation. We present an integrated framework that addresses several important test scheduling problems. We first present efficient techniques to determine optimal SOC test schedules with precedence constraints, i.e., schedules that preserve desirable orderings among tests. We then present a(More)
Core test wrappers and test access mechanisms (TAMs) are importantcomponents of a system-on-chip (SOC) test architecture.Wrapper/TAM co-optimization is necessary to minimize the SOC testingtime. Most prior research in wrapper/TAM design has addressedwrapper design and TAM optimization as separate problems, therebyleading to results that are sub-optimal. We(More)
Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and(More)