Vijay R. Sar-Dessai

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Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are abstracted to voltage behavior for use in voltage-level fault simulation and test generation. Fault simulation is done using different test sets in order to study their effectiveness. Test generation is done to detect the highest possible bridging(More)
This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We demonstrate that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we(More)
In this work' we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the $rst resistive bridging faylt(More)
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