Vida Vakilotojar

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This paper describes a tool-supported methodology for the register-transfer-level formal verification of a growing hardware design paradigm-timed asynchronous systems. These systems are a network of communicating asynchronous and synchronous components and have correctness constraints that depend on specified bounded delays. This paper formalizes the(More)
This paper describes the design and verification of a high-performance asynchronous differential equation solver. The design has low control overhead which allows the average-case delay to be 48% faster (tested at 22 C and 3.3V) than any comparable synchronous design (simulated at 100 C and 3V). The techniques to reduce completion sensing overhead and hide(More)
The goal of induced hierarchical verification techniques is to automatically create hierarchy in an originally flat circuit in order to decompose the verification problem (i.e., checking hazard-freedom and conformance to a specification) into that of verifying a set of smaller sub-circuits. Existing induced hierarchical verification techniques for(More)
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