Victor M. van Santen

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Technology scaling noticeably increases the susceptibility of transistors to varied degradations induced by aging phenomena like Bias Temperature Instability (BTI) and Time-Dependent-Dielectric Breakdown (TDDB). Therefore, estimating the reliability of an entire computational system necessitates investigating how such phenomena will ultimately lead to(More)
With technology in deep nano scale, the susceptibility of transistors to various aging mechanisms such as <i>Negative/Positive Bias Temperature Instability</i> (NBTI/PBTI) and <i>Hot Carrier Induced Degradation</i> (HCID) etc. is increasing. As a matter of fact, different aging mechanisms simultaneously occur in the gate dielectric of a transistor. In(More)
As feature sizes of transistors began to approach atomic levels, aging effects have become one of major concerns when it comes to reliability. Recently, aging effects have become a subject to voltage scaling as the latter entered the sub-&#x03BC;s regime. Hence, aging shifted from a sole long-term (as treated by state-of-the-art) to a short and long-term(More)
Bias Temperature Instability (BTI) is one of the key causes of reliability degradations of nano-CMOS circuits. While the long-term impact of BTI has been studied since years, the <i>short-term</i> implications of BTI on circuits are unexplored. In fact, in physics short-term BTI effects, i.e. instantaneous (i.e. sub <i>&mu;s</i>) frequency dependent(More)
<italic>Editor&#x2019;s note:</italic> Process variations, aging and wearout, are nonidealities that lead to suboptimal system performance and increased power. In order to understand the effects of these degradation effects, until now, researchers have investigated them thoroughly, but separately from each other. What this article shows is that process(More)
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