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Asynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. Very few analysis techniques or tools are available for estimating their performance. In this paper we adapt the theory ofGeneral-ized Timed Petri-nets (GTPN)for analyzing and comparing asynchronous circuits(More)
The basic building block of on-chip nanophotonic interconnects is the microring resonator [14], and these resonators change their resonant wavelengths due to variations in temperature — a problem that can be addressed using a technique called ”trimming”, which involves correcting the drift via heating and/or current injection. Thus far(More)
This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and high-throughput interconnections within a data center. DOS exploits wavelength routing characteristics of a switch fabric based on an Arrayed Waveguide Grating Router (AWGR) that allows contention resolution in the wavelength domain.(More)
—Designers are increasingly relying on field-pro-grammable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 12 and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding(More)
We present Synchroscalar, a tile-based architecture forembedded processing that is designed to provide the flexibilityof DSPs while approaching the power efficiency ofASICs. We achieve this goal by providing high parallelismand voltage scaling while minimizing control and communicationcosts. Specifically, Synchroscalar uses columnsof processor tiles(More)
Microring resonator-based photonic interconnects are being considered for both on-chip and off-chip communication in order to satisfy the power and bandwidth requirements of future large scale chip multiprocessors. However, microring resonators are prone to malfunction due to fabrication errors, and they are also extremely sensitive to fluctuations in(More)
Deep Convolutional Neural Networks (DCNN) have proven to be very effective in many pattern recognition applications, such as image classification and speech recognition. Due to their computational complexity, DCNNs demand implementations that utilize custom hardware accelerators to meet performance and energy-efficiency constraints. In this paper we propose(More)
The Ethernet switch is a primary building block for today's enterprise networks and data centers. As network technologies converge upon a single Ethernet fabric, there is ongoing pressure to improve the performance and efficiency of the switch while maintaining flexibility and a rich set of packet processing features. The OpenFlow architecture aims to(More)
We investigate the advantages and disadvantages of different loopback buffer architectures for optical switches and compare their performance via simulation. The simulation results show that, without the use of virtual output queuing, the head-of-line blocking can be alleviated by wavelength parallelism when each separate queue in a loopback buffer has(More)