Venkatesh Akella

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Asynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. Very few analysis techniques or tools are available for estimating their performance. In this paper we adapt the theory ofGeneralized Timed Petri-nets (GTPN)for analyzing and comparing asynchronous circuits(More)
The basic building block of on-chip nanophotonic interconnects is the microring resonator [14], and these resonators change their resonant wavelengths due to variations in temperature — a problem that can be addressed using a technique called ”trimming”, which involves correcting the drift via heating and/or current injection. Thus far(More)
This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and high-throughput interconnections within a data center. DOS exploits wavelength routing characteristics of a switch fabric based on an Arrayed Waveguide Grating Router (AWGR) that allows contention resolution in the wavelength domain.(More)
We present Synchroscalar, a tile-based architecture forembedded processing that is designed to provide the flexibilityof DSPs while approaching the power efficiency ofASICs. We achieve this goal by providing high parallelismand voltage scaling while minimizing control and communicationcosts. Specifically, Synchroscalar uses columnsof processor tiles(More)
Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This(More)
SHILPA is system for the high-level synthesis of self-timed circuits. It takes behavioral descriptions in a process+functional language called hopCP and produces a netlist for the Actel FPGA, supported by the VIEWlogic tools. hopCP descriptions are initially translated into an intermediate-form based on hypergraphs called HFG. SHILPA then applies action(More)
In this paper we investigate the problem of estiinating power consumption in an asynchronous (clockless) circuit. Specifically, we examine the differences in power estimation in synchronous and asynchronous circuits and propose to integrate and extend the recent work b y Devadas, Glzosh, and Keutzer to self-timed circuits. A Petri ne t based abstraction for(More)
The Ethernet switch is a primary building block for today's enterprise networks and data centers. As network technologies converge upon a single Ethernet fabric, there is ongoing pressure to improve the performance and efficiency of the switch while maintaining flexibility and a rich set of packet processing features. The OpenFlow architecture aims to(More)