Veeresh Pujari

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This paper proposes new processor architecture for accelerating data-parallel applications based on the combination of VLIW and vector processing paradigms. It uses VLIW architecture for processing multiple independent scalar instructions concurrently on parallel execution units. Data parallelism is expressed by vector ISA and processed on the same parallel(More)
BACKGROUND Spinal cord injury resulting from spinal anesthesia is a rare, but an alarming scenario. The most likely cause is believed to be misjudged level of intervertebral space (IVS). We evaluated the accuracy of palpation method to locate IVS with the ultrasonography. MATERIALS AND METHODS A total of 109 patients undergoing spinal anesthesia were(More)
Flip-flops is critical timing elements in digital circuits which have a large impact on the circuit speed and power consumption. The performance of flip-flop is an important element to determine the efficiency of the whole synchronous circuit. In an attempt to reduce power consumption in flip-flops a low-power flip-flop (FF) design featuring an explicit(More)
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