Vasilis F. Pavlidis

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Several interesting topologies emerge by incorporating the third dimension in the design of Networks-on-Chip (NoC). An analytic model for the zero-load latency of each network that considers the effect of the topology on the performance of a 3-D NoC is developed. A tradeoff between the number of nodes utilized in the third dimension of the network, which(More)
Three-dimensional (3-D) or vertical integration is a potent design paradigm to overcome the existing interconnect bottleneck in integrated systems. The major advantages of this emerging technology are the inherent reduction in wirelength and the ability to integrate heterogeneous circuits within a multi-plane system. To exploit these advantages, however,(More)
Three-dimensional (3D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3D clock distribution network topologies is presented in this paper. Experimental results of a(More)
Thermal issues are one of the primary challenges in 3-D integrated circuits. Thermal through-silicon vias (TTSVs) are considered an effective means to reduce the temperature of 3-D ICs. The effect of the physical and technological parameters of TTSVs on the heat transfer process within 3-D ICs is investigated. Two resistive networks are utilized to model(More)
3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled(More)
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location that minimizes the propagation delay of an interconnect line connecting two circuits on different(More)
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) circuits. As shown in this paper, these vertical interconnects provide additional low impedance paths for(More)
——A physical model for the design of the power distribution networks in three-dimensional integrated circuits is proposed. The tradeoffs among the different design parameters are specified and analyzed. Different case studies are explored, indicating that smaller and denser TSVs can deliver power more efficiently as compared to larger and coarsely(More)
The propagation delay of interlayer 3-D interconbeen described in the literature [5]-[7]. The delay expresnects is investigated in this paper. For RC interconnects sions included in these interconnect prediction models for 3connecting two circuits located on different physical planes, the D circuits are similar to traditional CMOS models,(More)
Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power(More)