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- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
- J. Electronic Testing
- 2004

- Daniel Larkin, Valentin Muresan, Noel E. O'Connor
- ISCAS
- 2006

This paper tackles the problem of accelerating The rest of this paper is organised as follows: section II motion estimation for video processing. A novel architecture details related prior research. Section III proposes a new binary using binary data is proposed, which attempts to reduce power motion estimation routine which exploits early termination… (More)

- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
- IEEE International Workshop on Rapid System…
- 2001

- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
- IEEE International Workshop on Rapid System…
- 2000

A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency having assigned power dissipation limits. Moreover, the algorithm… (More)

This paper proposes an efficient hardware architecture for an elementary function generator that is suitable for use as the activation function in an artificial neural network (ANN). A spline-based approximation function is designed that provides a good trade-off between accuracy and ...., whilst also being inherently scalable and adaptable to other… (More)

- Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow
- PATMOS
- 2004

This paper proposes an energy-efficient hardware acceleration architecture for the variable N-point 1D Discrete Cosine Transform (DCT) that can be leveraged if implementing MPEG-4’s Shape Adaptive DCT (SA-DCT) tool. The SA-DCT algorithm was originally formulated in response to the MPEG-4 requirement for object based texture coding, and is one of the most… (More)

- Andrew Kinane, Valentin Muresan, Noel E. O'Connor
- ISCAS
- 2006

The efficient design of multiplierless implementaThe goal is to find the optimal sub-expressions across all N dot tions of constant matrix multipliers is challenged by the huge products in (3) that lead to the fewest adder resources needed. solution search spaces even for small scale problems. Previous apThree properties aid the classification of… (More)

Classical scheduling approaches are applied here to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. List schedulinglike approaches are proposed j r s t as greedy algorithms to tackle the fore mentioned problem. Then, distributiongraph based approaches are described in order to achieve balanced test… (More)

- Valentin Muresan, Xiaojun Wang, Mircea Vladutiu
- ISCAS
- 2000

A left-edge algorithm approach is proposed in this paper to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the left-edge algorithm in order to improve the test concurrency under power dissipation limits. Test scheduling examples and… (More)