Vahid Kazempour

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Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs were shown to be more power efficient than conventional symmetric multicore processors, and it is therefore likely that future multicore systems will include cores of different(More)
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity is exploited by OS schedulers: they tend to reschedule processes to run on a recently used processor. On conventional (uni-core) multiprocessor systems, exploitation of cache(More)
In this position paper, we present our vision for the scheduling infrastructure in a many-core hypervisor – the hypervisor targeted for many-core platforms. The key objectives of our system are scalability and heterogeneity-awareness. We see these as first-order objectives, because future many-core processors will consist of thousands of cores and those(More)
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