Vahid Janfaza

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In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method(More)
Long test application time for a System on Chip (SoC) is a major problem in digital design testing. This problem mostly originates from large test data. High volume test data not only increases required ATE memory and bandwidth, but also increases test time. Test compression reduces test data volume without any impact on its coverage. This work proposes two(More)
Sequential circuit testing has been recognized as one of the most difficult problems in the area of fault detection. Controllability and observability of a sequential circuit is low because of their internal states. Therefore finding suitable sequence of test patterns is becoming increasingly complex. We have proposed a method to estimate an expectation(More)
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults(More)
This paper presents a hybrid history-based test generation mechanism that intermittently applies partial-test vectors to reduce test application time. Test generation is done by looking into the results of the circuit under test that are used later as a part of partial-test vectors. Therefore, these test vectors convey a history of previously applied tests.(More)
Future applications will require processors with many cores communicating through a regular interconnection network. As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system life time. In order to ensure the reliability of(More)
System designers are increasingly interested in the use of tools and methods letting them describe and simulate mixed signal systems. A pioneer description language for this purpose is VHDL-AMS. Due to special features of this language, the traditional method of analog-circuits analysis, the nodal analysis method that is used in most analog simulators, such(More)
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