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Journals and Conferences
The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip power delivery… (More)
On-chip PDN consists of power grid and the intentional decap. In this paper, we demonstrate a technique to determine the on-chip PDN model for a chipset. 2D TLM approach can be used up-to several GHz.
SI-PD co-modeling, co-simulation, and system response optimization are demonstrated that employ passive modeling of signals and power delivery networks to optimize the system response. Decomposition… (More)