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- Pradip Mandal, V. Visvanathan
- IEEE Trans. on CAD of Integrated Circuits andâ€¦
- 2001

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the givenâ€¦ (More)

- S. Ramanathan, V. Visvanathan
- VLSI Design
- 1996

Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolicâ€¦ (More)

- Pradip Mandal, V. Visvanathan
- VLSI Design
- 1997

Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise and cross-talk andâ€¦ (More)

- Dinesh Somasekhar, V. Visvanathan
- The Sixth International Conference on VLSI Design
- 1993

An 8 bit by 8 bit signed two's complement pipelined multiplier in 1.6Î¼m N well CMOS, capable of throughputs of 230 million multiplications per second, is described. A half bit level pipelinedâ€¦ (More)

- Linda S. Milor, V. Visvanathan
- IEEE Trans. on CAD of Integrated Circuits andâ€¦
- 1989

The IC fabrication process contains several testing stages. Because of the high cost of packaging, the testing stage prior to packaging, called waferprobe, is key in reducing overall manufacturingâ€¦ (More)

- B. Das, Bharadwaj S. Amrutur, H. S. Jamadagni, N.V. Arvind, V. Visvanathan
- IEEE Transactions on Semiconductor Manufacturing
- 2009

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuitâ€¦ (More)

- Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan
- 1993 International Conference on Parallelâ€¦
- 1993

The concept of supernodes has been widely used in the design of algorithms for the solution of sparse linear systems of equations. This paper discusses the use of supernodes in the design ofâ€¦ (More)

- S. Ramanathan, V. Visvanathan, S. K. Nandy
- Integration
- 1999

y This paper is an extended version of the results presented at VLSI Design'99 30]. a S. Ramanathan is currently with Philips Semiconductors, Bangalore Abstract ASICs ooer the best realization of DSPâ€¦ (More)

- V. Visvanathan, Linda S. Milor
- Symposium on Computational Geometry
- 1986

An efficient algorithm to determine the image of a parallelepiped under a linear transformation is presented. The work was motivated by certain problems in the testing of analog integrated circuits.â€¦ (More)

- P. Sadayappan, V. Visvanathan
- IEEE Trans. Computers
- 1988