V. Solberg

Publications24
h-index3
Citations35
Highly Influential Citations0
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Board level reliability testing of /spl mu/BGA/sup (R)/ packaging with lead-free solder attachment
  • V. Solberg
  • Engineering
    Proceedings of 3rd Electronics Packaging…
  • 5 December 2000
To maximize the benefit of chip-scale packaging for portable and handheld electronics, the user must consider efficient and cost effective assembly processing. Factors that an engineer should review…
Reliable and low cost wafer level packaging. Process description and qualification testing results for wide area vertical expansion (WAVE/sup TM/) package technology
A number of companies around the world are developing or have begun offering devices processed and packaged in the wafer format. Most of these competing concepts involve the creation of a…
Performance evaluations of stacked CSP memory modules
  • V. Solberg, G. Gray
  • Computer Science
    IEEE/CPMT/SEMI 29th International Electronics…
  • 14 July 2004
TLDR
The following will examine the company's /spl mu/Z/spl trade/-Ball Stack package configurations and future potential for higher density package technology will be outlined as it relates to trends in high density and high performance market needs.
Lead-free soldering for CSP : The impact of higher temperature SMT assembly processing
Many of the electronic products being developed using miniature chip-scale package are moving toward lead-free, environmentally safe assembly processes. Key factors that an engineer should evaluate…
High density stacked packaging solution for SiP applications: A flex based multiple die chip-scale package technology
The miniature chip-scale and chip-size BGA package offerings continue to furnish the solution for a majority of the newer portable electronics applications. Hand-held and wireless electronics has…
3D substrate innovation for complex high pin count flip-chip applications
Due to the increased complexity and greatly expanded I/O on today's multiple function semiconductors, IC suppliers have been forced to abandon the traditional wire-bond package assembly, opting…
Embedding Passive and Active Components : PCB Design and Fabrication Process Variations
Embedding components within the PC board structure is not a new concept. Until recently, however, most embedded component PC board applications adapted only passive elements. The early component…
High density substrate solution for complex high pin count flip-chip applications
There are a number of factors to consider when selecting an optimal semiconductor package configuration for the newer generations of high density controllers and processors; I/O requirement, package…
3D Packaging Solution Providing DDR & LPDDR Co-Support for Ultrabooks and Next Generation Servers
Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. To enable the new generations of processors to…
No-clean And Water-clean Mass Reflow Processes Of 0.4 mm Pitch, 256-Pin Fine Pitch Quad Flat Packs (QFP)
The water-clean and no-clean mass reflow processes of the 0.4 mm pitch, 28 mm body size, and 256-Pin fine pitch quad flat packs (QFP) are presented. Emphasis is placed on the fine pitch parameters…
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